The present invention relates to a semiconductor device and its manufacturing technique, in particular, to technology which is effective when applied to a semiconductor device having a MONOS (Metal Oxide Nitride Oxide Semiconductor) type nonvolatile memory cell and its manufacturing.
For example, in the twelfth embodiment of Japanese Patent Laid-Open No. 2004-303918 (Patent Document 1), a nonvolatile memory cell is disclosed, in which the erase speed is increased by constituting a memory gate electrode by a two-layer conductive layer and making the concentration of n-type impurity in the lower conductive layer lower than the concentration of n-type impurity in the upper conductive layer, and then erasing data by utilizing both the effect of the pulling-out of electrons in a charge storage layer and the effect of recombination of the electrons contributing to data storage with holes injected from the memory gate electrode side. From a similar idea, a technique is also disclosed, which forms a memory gate electrode by using a polycrystal silicon film having p-type impurities.
In International Patent Publication No. WO 02/043151 Pamphlet (Patent Document 2), a technique is disclosed, which causes tensile stress to occur in a channel formation region of an n-channel MISFET and causes compression stress to occur in a channel formation region of a p-channel MISFET by using a self-alignment silicon nitride film.